Product Description

The DCQ-2400 is a form, fit and function equivalent for the Digital IDV11-A (M5026). Like the IDV11-A, the DCQ-2400 is an isolated digital input module for the Qbus.  It accepts up to 16 single optically isolated inputs used for monitoring voltages where noise immunity or common mode rejection is important.  The 16 bit data are read by programs and transferred to the processor or memory.

The input line bit 15 is selectable by program and generates an interrupt at the leading edge (ON-going signal) and/or at the trailing edge (OFF-going signal).

The standard input range is 24 to 48 Vdc.  In this range, the input switching delay can be changed by a programmable contact bounce eliminator to three different values. In addition, a programmable low level input range for low speed, low power 5 Vdc signals and usable for TTL or MOS inputs is selectable.

The design uses DEC I/O interface circuits to interface to the Qbus and user signals plus a high density Field Programmable Gate Array (FPGA) for control circuitry.  The FPGA is designed using internal logic symbols in industry standard schematic form.  A serial prom loads the schematic symbols into the FPGA following each power up cycle.  The use of an FPGA allows ease of design verification through simulation, ease of design improvements and for factory updates when and if needed.

Key Features

• 16 single, optically isolated inputs
• Interrupt capability on input line bit 15
• Interrupt generating signal edge is programmable
• Programmable contact bounce eliminator
• Standard input range from 24 to 48 Vdc
• Programmable low level range for 5 Vdc signals
• Module identification code readable by program

Compatibility

• Connector, signal and diagnostic compatible with Digital I/O test connector module
• MDM diagnostic NAIDAA compatible
• XXDP diagnostic CZIXVxx compatible
• Qbus standard interface circuits (DS8641)
• User interface components are identical to the original design or electrical equivalents
• The internal circuitry is identical to the original Digital design but uses an FPGA to replace the individual gate-level components.
• Follows all Qbus rules and specifications as outlined in Digital’s LSI-11 Bus Spec, DEC Std 160 17-SEP-81.
• Qbus interrupt priority level jumper compatible with BR5, BR6 (W1, W2)
• Qbus address and vector switch compatible including switch location and settings